The present disclosure relates to techniques of increasing the speed of semiconductor memory devices.
When a memory having a large bit width is operated at high speed, an interconnect resistance, an interconnect capacitance, and a gate capacitance occurring during transmission of a control signal for an input/output circuit, such as a sense amplifier activation signal, a bit line precharge signal, a column decode signal, etc., increases, and therefore, a waveform has more difficulty in increasing or decreasing in further subsequent stages. To address this problem, there is a known technique of supplying a control signal via a repeater to increase the speed (see, for example, Japanese Patent Publication No. H11-353870).
In conventional memories having a typical configuration, an interconnect resistance, an interconnect capacitance, and a gate capacitance occurring during transmission of a control signal for an input/output circuit, such as a sense amplifier activation signal, a bit line precharge signal, a column decode signal, etc., increase with an increase in the bit width, and therefore, it is difficult to increase the speed.
Moreover, when a repeater is employed as in Japanese Patent Publication No. H11-353870, the repeater is provided in a region other than regions in which a sense amplifier or a column decoder is provided and which have a pitch corresponding to that of memory cells. Therefore, memory cells cannot be provided around the repeater, and therefore, a region around the repeater is dead space. The increase in the speed thus leads to an increase in the area.